As is known in the art, traditionally in the microelectronics industry, electrical devices are fabricated on wafers and then diced into individual chips. The bare chips would then get assembled with other components into a package for environmental and mechanical protection. In commercial applications, the chips were generally assembled into plastic packages. In military applications, where electronics are generally exposed to harsher environments, the parts are generally housed in a hermetic module. Such packages or modules would then be further assembled unto circuit boards and systems. However, as electronic systems advance, there is a need to increase functionality while decreasing the size and cost of components and sub-systems.
One way to reduce size and cost is to create packages at the wafer level and then subsequently dicing the wafer into individual packaged semiconductors (i.e., wafer-level packaging). Many methods have been suggested to create wafer-level packages. One method, call wafer bonding, is to bond a wafer with pre-formed cavities over the device wafer. The bonding can be achieved through thermal bonding, adhesive or solder bonding, see for example, Rainer Pelzer, Herwig Kirchberger, Paul Kettner, “Wafer-to Wafer Bonding Techniques: From MEMS Packaging to IC Integration Applications”, 6th IEEE International Conference on Electronic Packaging Technology 2005 and A. Jourdain, P. De Moor, S. Pamidighantam, H. A. C. Tilmans, “Investigation of the Hermeticity of BCB-Sealed Cavities For Housing RF-MEMS Devices”, IEEE Electronic Article, 2002.
However, this method introduces a lot of complexity into the process. Thermal bonding is generally achieved at very high temperatures, in excess of 400 C. Adhesive bonding can be achieved at lower temperature, but adhesive outgassing is a concern. Therefore wafer bonding is not a suitable and cost-effective method for some applications.
Another approach is to use Liquid crystal polymer (LCP). It has recently become a popular candidate for various packaging approaches, due to its excellent electrical, mechanical and environmental properties. The material comes in rolls and can be laminated unto the wafer as a film. A general method is to use multiple stacks of LCP. Individual holes were created in a layer of LCP and laminated over the wafer so that the device or FETs are exposed through the holes. This first layer of LCP forms the sidewall of the cavity. Then a second layer of LCP is laminated over the entire wafer, thus enclosing the cavity, see Dane. C. Thompson, Manos M. Tentzeris, John Papapolymerou, “Packaging of MMICs in Multilayer of LCP Substrates,” IEEE Microwave and Wireless Components Letters, vol. 16, No. 7, July 2006. Single stack of LCP can also be used, but cavities still must be formed on the material before lamination unto wafer, see Dane. C. Thompson, Nickolas Kinglsley, Guoan Wang, John Papapolymerou, Manos M. Tentzeris, “RF Characteristics of Thin Film Liquid Crystal Polymer (LCP) Packages for RF MEMS and MMIC Integration”, Microwave Symposium Digest, 2005 IEEE MTT-S International, 12-17 Jun. 2005 Page(s):4 pp. and Mogan Jikang Chen, Anh-Vu H. Pham, Nicole Andrea Evers, Chris Kapusta, Joseph Iannotti, William Komrumpf, John J. Maciel, Nafiz Karabudak, “Design and Development of a Package Using LCP for RF/Microwave MEMS Switches”, IEEE Transactions on Microwave Theory and Techniques, vol. 54, No. 11, November 2006. The prior work mentioned above requires very accurate alignment during wafer bonding which limits the flexibility to create small cavities that cover just the active devices and individual passive components. Generally, with a larger cavity, not only is the risk for mechanical failure is greater, environmental protection of the package may also be compromised, see Aaron Dermarderosian, “Behavior of Moisture in Sealed Electronic Enclosures,” International IMAPS conference in San Diego, October of 2006. These issues with traditional methods limit the manufacturability and performance of the package.
In multichip-module packaging approaches, the chips are packaged by spinning or laminating the dielectric film over the entire chip. Prior work have been done using various combination of Kapton E, BCB, SPIE, etc., see Vikram B. Krishnamurthy, H. S. Cole, T. Sitnik-Nieters, “Use of BCB in High Frequency MCM Interconnects”, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 19, No. 1, February 1996. A dielectric film deposited directly on top of transistors generally degrades its performance due to the increased parasitic capacitance. The multichip-module packaging is a chip-level rather than a wafer-level approach.
In another wafer-level packaging approach, caps made from different material, such as LCP, glass, etc. were dropped unto the wafer to cover individual chips. The caps were sealed in place using adhesives. Again, this is a complex process that picks and places the caps on individual chips; see George Riley, “Wafer Level Hermetic Cavity Packaging”, http://www.flipchips.com/tutorial43.html.
Another method and package is described in U.S. Pat. No. 8,035,219 entitled, “Method for Packing Semiconductors at a Wafer Level”, inventor William J. Davis, Ward G. Fillmore, and Scott MacDonald, issued Oct. 11, 2011 assigned to the same assignee as the present invention.
In accordance with the present embodiment, a method is provided for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: forming device exposing openings and electrical contact exposing opening in a dielectric layer disposed on the surface portion of the semiconductor wafer to expose the devices and electrical contacts pads, respectively; and depositing a porous material in the device exposing openings over the devices.
In one embodiment, a package is provided for a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.
In one embodiment, the dielectric layer is a lithographically processable material.
In one embodiment, the package includes a second dielectric layer deposed over the first-mentioned dielectric layer and over the porous material.
In embodiment, the second dielectric has openings in registration with the electrical contact exposing opening.
In one embodiment, the second dielectric layer is a lithographically processable material.
In one embodiment, a package is provided for a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a first dielectric layer comprising a first lithographically processable material disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad such one of the devices; a porous material in the device exposing opening over said one of the devices; and a second dielectric layer comprising a second lithographically processable material disposed on the porous material and on selected regions of the first dielectric layer and absent from the electrical contacts pad opening of the first dielectric layer.
In one embodiment, the porous material is an aerogel.
In one embodiment, the porous material is an aerogel-polymer.
In one embodiment, the porous material is greater than 95 percent air by solid.
In one embodiment, the porous material has a porosity in the range of 60-95 percent air.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.